1. Field of the Invention
The present invention relates generally to a doped, passivated graphene nanomesh, and more particularly, a doped, passivated graphene nanomesh which includes a passivating element and a dopant bonded to the passivating element.
2. Description of the Related Art
Current technology depends on decreasing the size of the transistor to make computers more powerful, faster and more energy efficient. As current efforts approach the miniaturization limit (the size of a single atom), alternative technologies are needed to continue improving integrated circuit performance. Optimization is carried on multiple fronts such as developing alternative architectures, new materials, new algorithms and new software.
FIG. 1A illustrates a graphene sheet 110, according to an exemplary aspect of the present invention. Graphene is a candidate material for semiconductor fabrication. It is a hexagonal lattice (e.g., a honeycomb) of carbon atoms (e.g., a two-dimensional network of single layer carbon atoms). It is a semimetal in that its conduction and valence bands just meet at discrete points in the Brillouin zone. It is an interesting of mix of semiconductor (zero density of states) and metal (zero bandgap).
An electron in graphene has an effective mass of zero and behaves more like a photon than a conventional massive particle. Graphene can carry huge current densities—about 108 A/cm2, which is roughly two orders of magnitude greater than copper.
A graphene layer may be epitaxially grown on any lattice-matched material, and has been used for many electronic applications. Such applications require the graphene to be doped to make it a semiconducting material. Conventionally, graphene is doped by adsorbing volatile compounds to its surface.
FIG. 1B illustrates a conventional field effect transistor (FET) 100 which includes the graphene sheet 110 (e.g., a graphene layer 110) epitaxially formed on and lattice-matched to, a single crystal insulative layer 120.
Separate portions of layer 110 form source region 110a and drain region 110b. Schematically depicted source and drain electrodes Vs and Vd, respectively, make electrical contact with source and drain regions 110a and 110b. A third portion of layer 110 forms a channel region 110c, which couples the source and drain regions to one another. The channel region 110c may include, for example, a doped graphene layer.
As is well known in the semiconductor and graphene device arts, the resistance/conductance of the channel region 110c is controlled by a gate 130 which includes a patterned gate insulator 130a disposed on channel region 110c and a gate electrode 130b formed on gate insulator 130a. Finally, a common (often grounded) electrode 140 is formed on the bottom of insulative layer 120.
In operation, when suitable voltages Vs and Vd are applied to the source and drain electrodes, respectively, current flows or is inhibited from the source region 110a to the drain region 110b (or conversely) depending on the gate voltage applied between electrodes 130b and 140. When the gate voltage Vg is sufficient to reduce electron transport by depleting the channel region 110c, the channel resistance increases and current flow decreases, and conversely.